In the case of a binary tunneling based static random access memory (TSRAM) cell, prior technology used one tunnel diode connected to a load transistor, where the connection point between the devices is the sense node (Vout). In this example, the load transistor is an enhancement mode NFET, although a depletion mode NFET could be used. The drain of the load NFET is placed at some positive bias (Vds) greater than the Vhigh (the “1” state that the TSRAM cell latches into). The gate of the load NFET is placed at some value (Vgs) such that the current-voltage (I-V) curve of the load NFET crosses the negative differential resistance (NDR) region of the tunnel diode. This is called the standby state.
By increasing Vgs such that the I-V curve of the load NFET is higher than the peak current of the tunnel diode, this I-V curve now intersects the tunnel diode I-V curve at one point (rather than three, two of which are stable, in the standby state). Decreasing Vgs back to the standby value results in the TSRAM cell latching into the Vhigh state. Likewise, switching Vgs to a value such that the load NFET I-V curve drops below the valley current of the tunnel diode, and then back to the standby value, latches the TSRAM cell in to the Vlow (logic low, or “0”) state. This approach is called the dynamic load approach, because Vgs of the load NFET is varied, and from an architectural standpoint, the static load approach is supposedly better. The load NFET also can be replaced by a resistor or tunnel diode.
In the static load approach, the same circuit is used, except that a “driver” FET is placed at Vout, and this driver FET acts as a source or sink of current. In doing so, additional current is forced through the tunnel diodes in one direction or another, effectively shifting the tunnel diode I-V characteristic up or down to achieve the same result. In this case, however, Vgs of the load NFET is held constant (hence the term “static load”).